A particular (fictional) CPU has the following internal units and timings (WR and RR are write/read registers, ALU does all logic and integer operations and there is a separate floating point unit. ID - instruction fetch and decode 180ps RR - read registers 40ps WR - write registers 60ps ALU - arithmetic and logic 180ps FPU - floating point 280ps MEM - memory access 200ps There are 6 basic instruction types: LOAD: ID + RR + ALU + MEM + WR: 660ps, STORE: ID + RR + ALU + MEM: 600ps MEMOP: ID + WR + RR + ALU + MEM: 660ps LOGIC/INTEGER: ID + RR + ALU + WR: 460ps FLOATING POINT: ID + RR + FPU + WR: 560ps BRANCH: ID + RR + ALU: 400ps 1 cycle is 660ps for this machine, on the assumption that all instructions take 1 cycle (ignore memory delays). Outline what a pipeline would look like: Give number of stages operations in each stage new clock rate speedup compared to original 660ps instruction rate with no pipeline. Assume you double the number of registers, but increased address complexity would add 10ps to RR, and 15ps to WR. What (if any) changes would you make to your pipelined machine (e.g. clock or stages or both)