A pipelined processor has the following features: Four pipeline stages: fetch instruction (FI), decode instruction (DI), calculate and fetch memory operands (FO), and execute instruction and store memory operands (EI). Register operands are accessed for read/write) by El stage. Memory ports: one read port and one write port. Branch prediction: based on takenot-taken switch as described in class (assume that we start at not-taken state). Suppose the processor executes the following loop, and assume that the memory location referenced by R1 has a value of 60 (decimal) initially: Instruction No Instruction 11 LOOP: DEC (R1) /* [R1] + [[R1]] - 1 */ I2 JNZ (R1), LOOP /* Jump to LOOP if [[R1]] # 0 */ 13 14 15 (a) Draw a timing diagram to show instruction pipelining during the first four iterations of the loop. Make sure you take care of hazards. (b) How many clock cycles are needed to execute this loop until it ends