a processor with 32-bit virtual addresses, 4K-byte pages, and 36-bit physical addresses. Assume memory is byte-addressable.

L1 data cache: 32K bytes, 64-byte blocks, 2-way set associative, indexed and tagged with physical address, write-back.

4-way set associative TLB with 128 entries in all. Assume the TLB keeps a dirty bit, a reference bit, and three permission bits (read, write, execute) for each entry.

Specify the number of offset, index, and tag bits for data cache and TLB.