A RISC processor has an eight stage pipeline: F D O E$1$ E$2$ MR MW WB $($fetch$,$ decode, register read operands, execute $1,$ execute $2,$ memory read, memory write, result writeback to register$).$ Simple logical and arithmetic operations are complete by the end of E$1.$ Multiplication is complete by the end of E$2.$ Assume that internal forwarding is possible and an operand can be used as soon as it is generated. Show the execution of the code:

LDR r$0,[$r$2]$

ADD r$3,$r$0,$r$1$

MUL r$3,$r$3,$r$4$

ADD r$6,$r$5,$r$7$

STR r$3,[$r$2]$

ADD r$6,$r$5,$r$7$