A "second chance cache (SCC) is a hardware cache designed to decrease conflict misses and improve hit latency for direct-mapped L1 caches. It is employed at the refill path of an L1 data cache, such that any cache line (block) which gets evicted from the cache is cached in the SCC. In the case of a miss in L1, the SCC cache is looked up (in some implementations, the SCC and L1 cache are looked up in parallel but we omit that possibility in this question). If the resulting access is a hit in the SCC, the line is transferred to L1. (b) One designer suggests to employ a direct-mapped L1 cache of (A+B) KB, instead of employing a direct-mapped L1 cache of A KB and an SCC of B KB. Are you in favor of this suggestion? Why? Or why not? [4 points] (c) Give a sample data access sequence that is not good for the SCC. Explain clearly why it is not good. [4 points] (d) Do you think an SCC should be direct-mapped or set-associative? Why? [4 points] (e) Do you think an SCC can be used along with an L2 or L3 cache as well? Explain. [4 points] A "second chance cache (SCC) is a hardware cache designed to decrease conflict misses and improve hit latency for direct-mapped L1 caches. It is employed at the refill path of an L1 data cache, such that any cache line (block) which gets evicted from the cache is cached in the SCC. In the case of a miss in L1, the SCC cache is looked up (in some implementations, the SCC and L1 cache are looked up in parallel but we omit that possibility in this question). If the resulting access is a hit in the SCC, the line is transferred to L1. (b) One designer suggests to employ a direct-mapped L1 cache of (A+B) KB, instead of employing a direct-mapped L1 cache of A KB and an SCC of B KB. Are you in favor of this suggestion? Why? Or why not? [4 points] (c) Give a sample data access sequence that is not good for the SCC. Explain clearly why it is not good. [4 points] (d) Do you think an SCC should be direct-mapped or set-associative? Why? [4 points] (e) Do you think an SCC can be used along with an L2 or L3 cache as well? Explain. [4 points]