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A sequence SR = 0 0 1 0 0 1 0 0 is applied to the inputs of an SR latch. Assume that initially the

A sequence SR

= 00 10 01 00

is applied to the inputs of an SR latch. Assume that initially the SR

latch is in the set state. If the clock is continuously asserted to logic

1,

what will be the output

sequence?

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