A sequential circuit has two pulse inputs, x1 and x2. The output of the circuit becomes 1 whenever the pulse sequence x1,x1,x2,x2,x2,x1 is detected. The output then remains 1 for all subsequent x1 pulses until an x2 pulse occurs.

(a) Derive a minimal state table describing the circuit operation. (Here you need to define the states and then perform state reduction).

(b) Synthesize the circuit using SR latches in the master rank. (Here, you need to make state assignment, generate excitation table and then perform logic minimization)