A special purpose microprocessor performs the following sequence of operations repetitively: i. Fetch an instruction from memory, ii. Decode it, iii. Fetch two operands A and B, iv. Execute the instruction and v. Write the result to memory The decode and execute operations take a clock cycle each. Each read or write from/to the memory takes 3 clock cycles. We propose to add a fast on-chip cache for all memory accesses to speed up its operation. A read from or a write to the cache can be done in a single clock cycle. The internal data paths are so designed that up to two data operands can be fetched together in a single clock cycle, if found in the cache. However, the bus to the main memory permits only a single read/write, which takes 3 clock cycles. (Notice that it is possible that one operand is in the cache but not the other. In this case the two operand fetches will proceed in parallel - one from the cache and the other from the external memory.) a) Assume that the probability of finding any address (for instruc- tion, operand or the result) in the cache is P. Find the average number of clock cycles taken for completing an instruction on the microprocessor. The answer must be given as a fully simplified function of P. b) What should be the value of P if we want to cut the average time taken for instruction execution to half (as compared to operation without cache). c) An empirical model relates the cache size to the probability of finding an address in it as: Cache Size (in KB) = P/(1-P). What cache size should we use to cut the average instruction ex- ecution time to half?