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A system with a processor frequency 50 MHz handles two interrupt lines and one polling line. Events on line INTERRUPT 1 have a minimal

A system with a processor frequency 50 MHz handles two interrupt lines and one polling line. Events on line

A system with a processor frequency 50 MHz handles two interrupt lines and one polling line. Events on line INTERRUPT 1 have a minimal inter-arrival time of 5 us, and their processing takes 30 cycles. Events on line INTERRUPT 2 are independent of those on INTERRUPT 1, and have a minimal inter-arrival time of 2 us, while their processing takes 10 cycles. An overhead of 5 cycles is needed for handling every interrupt event. Finally, a polling task is executed every 12 s, and its execution time is independent of whether or not an event arrived on the polling line. The polling task checks on the arrival of the polling event only when it starts execution. 1. (7 points) Determine the worst case processing time of the polling task, in cycles, such that processing of an event on the polling line finishes within 15 us after its arrival. Assume the minimal inter-arrival time of events is 15 s. 2. (3 points) Assume now that the polling task needs 50 cycles to execute. Determine tight lower and upper bounds on the average system utilization, including polling and interrupt tasks.

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