A uniprocessor has an L1 and an L2 cache. With no cache misses, the processor achieves an average CPI of 1. Suppose that in reality an L1 miss occurs every 50 cycles and that an L2 miss occurs every 500 cycles. The L1 miss penalty is 40 cycles and the L2 miss penalty is 400 cycles. The L2 cache is referenced only after a miss in the L1 cache. What is the effective (i.e., average) CPI rating for the processor with these cache miss rates?