(a.2) Fill in the current status of the scoreboard below. That is, Il is in the execute stage, 12 has read its operandi but not yet begun its execution, and each instruction (13, 14, 15) that can be issued has been issued but has not ye read its operands. 1) Instruction Status Quelle Issued? Operands Read? 1. (20 pts) Suppose we are using scoreboarding to dynamically schedule code. We have five functional units: 2 ALU's for integer operations including loads and stores for both integer as well as floating point values), 1 floating point addition and subtraction unit, 1 FP multiplication unit, and 1 FP division unit. The execution stage latencies for the various functional units are shown below. Consider the following program: Function units cycles instruction no. instructions instruction type FU1 (ALU ADDI R4, R4, #4 Integer integer) FU2 (ALU ADDF F5, F3, FO Float integer) FU3 (FP LF F3, 400(R4) Integer add/subtract) FU4 (FP MULTF F5, F3, multiplication) FUS (FP division) 15 DIVF F2, F4, Execution Complete? Results Written? Instruction II: ADDI R4, R4. #4 12: ADDF F5, F3, FO 13: LF F3, 400(R4) 14: MULTF F5, F3, FO 15: DIVF F2, F4, F5 Float FO Float 2) Functional Unit Status Busy? Op Dest Sourcel | Source2 Unit Unit 2 Rdyl? | Rdy2? 1. (20 pts) Suppose we are using scoreboarding to dynamically schedule code. We have five functional units: 2 ALU's for integer operations including loads and stores for both integer as well as floating point values), 1 floating point addition and subtraction unit, I FP multiplication unit, and I FP division unit. The execution stage latencies for the various functional units are shown below. Consider the following program: FU# FUI() FU2(12) FU3(+/-) FU4(0) FUSO Function units cycles instruction instructions instruction type no FUI (ALU integer) FU2 (ALU integer) FU3 (FP add subtract) FU4 (FP multiplication) FUS (FP division) ADDI R4, R4. #4 ADDF F5. F3.FO LF F3.400(R4) MULTF F5, F3, FO DIVF F2, F4, F5 Integer Float Integer Float Float 3) Register Result Status Reg FO FI F2 F3 F4 FS RO RI R2 R3 R4 Suppose that the first instruction (II) is currently in the execute stage. The second instruction (12) has issued but its operands have not yet been read. Assume that at the start of this code fragment, no functional unit is computing values targeted for FO and F3 (so 12's operands are ready). 4) Finish up all cycles and fill the instruction status queue with cycle numbers. (.1) For each of the remaining instructions (13, 14, 15), determine whether the instruction can be issued. If it cannot be issued, explain why not, Can 13, "LF F3, 400(R4)", be issued? YES_NO_ If not, why not? Can 14, "MULTF F5, F3, FO", be issued? YES_NO If not, why not? Can 15, "DIVF F2, F4, F5", be issued? YES_NO If not, why not? (a.2) Fill in the current status of the scoreboard below. That is, Il is in the execute stage, 12 has read its operandi but not yet begun its execution, and each instruction (13, 14, 15) that can be issued has been issued but has not ye read its operands. 1) Instruction Status Quelle Issued? Operands Read? 1. (20 pts) Suppose we are using scoreboarding to dynamically schedule code. We have five functional units: 2 ALU's for integer operations including loads and stores for both integer as well as floating point values), 1 floating point addition and subtraction unit, 1 FP multiplication unit, and 1 FP division unit. The execution stage latencies for the various functional units are shown below. Consider the following program: Function units cycles instruction no. instructions instruction type FU1 (ALU ADDI R4, R4, #4 Integer integer) FU2 (ALU ADDF F5, F3, FO Float integer) FU3 (FP LF F3, 400(R4) Integer add/subtract) FU4 (FP MULTF F5, F3, multiplication) FUS (FP division) 15 DIVF F2, F4, Execution Complete? Results Written? Instruction II: ADDI R4, R4. #4 12: ADDF F5, F3, FO 13: LF F3, 400(R4) 14: MULTF F5, F3, FO 15: DIVF F2, F4, F5 Float FO Float 2) Functional Unit Status Busy? Op Dest Sourcel | Source2 Unit Unit 2 Rdyl? | Rdy2? 1. (20 pts) Suppose we are using scoreboarding to dynamically schedule code. We have five functional units: 2 ALU's for integer operations including loads and stores for both integer as well as floating point values), 1 floating point addition and subtraction unit, I FP multiplication unit, and I FP division unit. The execution stage latencies for the various functional units are shown below. Consider the following program: FU# FUI() FU2(12) FU3(+/-) FU4(0) FUSO Function units cycles instruction instructions instruction type no FUI (ALU integer) FU2 (ALU integer) FU3 (FP add subtract) FU4 (FP multiplication) FUS (FP division) ADDI R4, R4. #4 ADDF F5. F3.FO LF F3.400(R4) MULTF F5, F3, FO DIVF F2, F4, F5 Integer Float Integer Float Float 3) Register Result Status Reg FO FI F2 F3 F4 FS RO RI R2 R3 R4 Suppose that the first instruction (II) is currently in the execute stage. The second instruction (12) has issued but its operands have not yet been read. Assume that at the start of this code fragment, no functional unit is computing values targeted for FO and F3 (so 12's operands are ready). 4) Finish up all cycles and fill the instruction status queue with cycle numbers. (.1) For each of the remaining instructions (13, 14, 15), determine whether the instruction can be issued. If it cannot be issued, explain why not, Can 13, "LF F3, 400(R4)", be issued? YES_NO_ If not, why not? Can 14, "MULTF F5, F3, FO", be issued? YES_NO If not, why not? Can 15, "DIVF F2, F4, F5", be issued? YES_NO If not, why not
