A.3 [10] Compute the effective CPI for an implementation of a RISC-V CPU using Figure A.29. Assume we have made the following measurements of average CPI for each of the instruction types: Clock cycles 1.0 3.5 Instruction All ALU operations Loads Stores Branches Taken Not taken 2.8 2.0 2.4 Jumps Average the instruction frequencies of gobmk and mef to obtain the instruction mix. You may assume that all other instructions (for instructions not accounted for by the types in Table A.29) require 3.0 clock cycles each. Program Stores Jumps astar Loads 28% 20% 17% ALU operations 46% 54% 36% 7% 23% 12% 219 50% 455 bzip gee gobmk h264ref hmmer libquantum mef omnetpp 33% 28% 16% 35% 23% 25% 19% 30% 9% 6% 11% 15% 14% 7% 8% Branches 18% 11% 20% 14 5% 17% 29% 24% 17% 15% 15% 27% 7% 46% 48% 29% 31% 399 56% 31% Sjeng xalancbmk Figure A.29 RISC-V dynamic instruction mix for the SPECint2006 programs. Omnetpp includes 7% of the instruc- tions that are floating point loads, stores, operations, or compares: no other program includes even 1% of other instruction types. A change in gcc in SPECint2006, creates an anomaly in behavior. Typical integer programs have load frequencies that are 1/5 to 3x the store frequency. In gcc, the store frequency is actually higher than the load frequency! This arises because a large fraction of the execution time is spent in a loop that clears memory by storing x0 (not where a compiler like gcc would usually spend most of its execution time!). A store instruction that stores a register pair, which some other RISC ISAs have included, would address this issue