According to the AVR Instruction Set Manual AVR datasheet, the instruction sequence below could suffer from a delay in pipeline sequencing and thus not result in the time between each instruction completing to be one cycle. What may explain the cause of the delay in pipelining? clr r27; Clear X high byte Idi r26,0x60, Set X low byte to 0x60 in r25,0x16; Read Port B cir r18; clear r18 Id r16,X, Load r1 with data space loc. 0x61 O Data Dependency O Memory Delay O Branch delay