design a memory decoder circuit. a) You are building an application specific digital device (ASDD) that needs to hold 256-bits of data (8-bits wide by 32 words) in a volatile memory. The only available memory units are 64-bits (8-bits wide by 8 words). Design a memory decoder for this custom digital system by deriving the logic expressions. From the memory user's perspective, they should be able to use 256-bits as a contiguous memory block. For this part design only the ASDD memory decoder and then clearly state i) how many bits are required for memory decoding, ii) how many bits are required for addressing, and iii) provide an example of how a user would access address 3 in memory (show decode-bits:address-bits). Your decoder must be designed using digital design methodology from lecture and labs (truth table, k-map, and minimized Boolean functions). You may not use predesigned integrated circuits elements for the decoder (e.g., MUX, Encoder, Decoder, etc.). [10 marks] b) Based upon part-a, very neatly draw your 256-bit memory design's digital circuit using standard logic symbols. For the 8x32 memory ICs you may represent them as a functional unit/block with clearly labelled pins that show: address pin(s), enable pin(s), read/write pin(s), input(s), output(s). Do not draw the memory ICs at the flip- flop level. Cleary label all inputs and outputs. You may assume the complement of any variable is readily available. [5 marks]