ALL PARTS WORK TOGETHER.

I will not accept answers that dont have a 1,2, and 3.

1: Consider the Intrinsity FastMATH TLB and cache implementation. The original design uses a 32 bit virtual memory address and a 32 bit physical memory address. Using a 4096 bytes (4 Kib) page size, each physical page number consists of 20 bits. Now assume that physical disk addresses are small enough to fit in the same number of bits as a physical memory address (e.g. for this problem it's 32 bits). How many bits would it take to implement a full page table for this virtual memory scheme? Include valid bits, dirty bits, reference bits, and the space for physical/disk addresses in your calculation. For simplicity, assume that every virtual page number needs a corresponding page table entry (PTE).

2: Now suppose the Intrinsity Fast Math processor is redesigned using an 8 KiB page size. Assume that physical disk addresses are small enough to fit in the same number of bits as a physical memory address. Assuming each virtual page number needs a corresponding PTE, how many bits would it take to implement a full page table for this virtual memory scheme?

3: Using C or C++, implement a program that will automatically perform the calculations which you had to manually compute in order to solve questions 1 and 2. You may still assume that disk addresses require the same number of bits as physical memory addresses. Your program will print the number of bits that would be required to implement the full page table.

You must accept several arguments on the command line (in this exact order):