all question with diagram in copy

CA2 TOPIC DISTRIBUTION (Computer Architecture) 1) A) Define Instruction Format, Instruction Set \& Instruction Cycle for zero address, one address, two address and three address with suitable example. B) Consider a pipeline having 4 phases with duration 60, 50, 90 and 80ns. Given latch delay is 10ns. Calculate- 1. Pipeline cycle time 2. Non-pipeline execution time 3. Speed up ratio 4. Pipeline time for 1000 tasks 5. Sequential time for 1000 tasks 6. Throughput C) Demonstrate space-time diagram for A[i]B[i]+C[i] for i=1 to . 2) A) There are two D1 and D2 pipeline processor. D1 has 5 stage pipeline with execution time of 3ns,2ns,4ns,2ns and 3ns. While the design D2 has 8 pipeline stages each with 2 ns execution time. How much time can be saved using design D2 over design D1 for executing 100 instructions? B) Explain Floating point addition using arithmetic pipeline with flow chart and steps of X=0.6213104 and Y=0.3510103 two numbers. C) Consider a 4 stage pipeline processor. Find with space-time diagram the number of cycles needed by the four instructions 11,12,13 and 14 in stages S1, S, S3 and S4 is shown below