An alternative form of the S$$R latch has the same structure as Figure $11\mathrm{.}22$ but uses

NAND gates instead of NOR gates.

a$.$ Redo Table $11\mathrm{.}10$a and $11\mathrm{.}10$b for S$$R latch implemented with NAND gates.

b$.$ Complete the following table, similar to Table $11\mathrm{.}10$c$.$