An alternative to both single-cycle and pipelined designs is the multi-cycle design. In a multi-cycle design, only one instruction executes at a time, but, like in a pipelined design, in a given cycle, only part of an instruction is executed, but at a much higher clock rate, and with a variable number of cycles per instruction (only the stages needed by a given instruction are used). e.g. in the table given, a load would take 5 cycles to complete, but an add would only take 4 Assuming that your multi-cycle design has a clock period of 200ps and your single-cycle design has a period of 800ps (as per the table) and there are no memory misses or other stalls (i.e. ideal CPI for both designs), what would be the speedup offered by a multicycle design if the distribution of instruction types was: R-Type 50% Load 20% Store 10% Branch 20% Jump 0% 0.25 4 3.14159