1. An arithmetic logic unit (ALU) is the center of a central processing unit (CPU). It performers a set of arithmetic and logical micro operations on two input buses at every rising edge of CLK input signal. An active high RST input is used to synchronously reset the output signal Y to logical zeros. The output Y must be available at every rising edge of CLK and the latencies for all functions is 1 cycle.

Inputs of ALU: CLK, RST, 8-bit unsigned A, 8-bit unsigned B, 4-bit unsigned SEL

Output of ALU: 8-bit unsigned Y

Function table of ALU is given below:

Function Number	SEL	Operation	Function
1	0000	Y<=A	Transfer A
2	0001	Y<=A+B	Addition
3	0010	Y<=A+Bbar	A plus 1s complement of B
4	0011	Y<=A and B	Logical AND
5	0100	Y<=A or B	Logical OR
6	0101	Y<=A xor B	Logical XOR
7	0110	Y<=Abar	Complement A
8	0111	Y<=shl A	Shift left A
9	1000	Y<=shr A	Shift right A
10	1001	Y<=0	Transfer 0s

The whole functions can be implemented using a single case statement even if it is not an optimal way of doing it. You are free to implement them in your way. You can ignore the carryout in addition operations.

1. Implement the given ALU entity in VHDL language. Provide your VHDL code.
2. Implement the given ALU module in Verilog language. Provide your code.
3. Implement the given ALU using OpenLane Design Flow.

Hint: Install OpenLane and Magic tools into your Linux machine as described in the class. Create required design files (alu.v, config.tcl and sky130A_sky130_fd_sc_hd_config.tcl) and run the following commands those are also described in the class.

Go to OpenLane folder

$cd ~/Openlane

$sudo make mount

Now Openlane docker is started

%./flow.tcl -design alu -init_design_config

This command creates an alu folder under /designs folder

Copy and modify the design files to this folder same as other example designs

./flow.tcl interactive

%package require openlane 0.9

%prep -design alu

%run_synthesis

%run_floorplan

%run_placement

%run_cts

%run_routing

%run_magic

%run_magic_spice_export

%run_magic_drc

%run_lvs

%run_antenna_check

After completion of flow without any error you can run magic to see GDSII of your design. Open a new terminal and run the following commands. Make sure nor error is generated throughout the flow.

Go to this folder

$cd ~/Openlane/designs/counter/runs/.. /results/finishing

Run magic

$magic -T sky130A lef read ../../tmp/merged.lef def read alu.gds &

In the first part of design, lets make the DIE_AREA is absolute and 100umx100um and set clock frequency to 200MHz. You can do it by setting the following parameters.

set ::env(CLOCK_PERIOD) x set ::env(FP_SIZING) absolute

set ::env(DIE_AREA) 0 0 100.0 100.0

Provide the screenshot of GDSII file for designed ALU. Provide synthesis statistics, and STA (setup time and hold time analysis) results. They can be found at the following directories:

~/Openlane/designs/alu/runs/name_of_run/reports/synthesis

~/Openlane/designs/alu/runs/name_of_run/logs/synthesis

In the second part, lets change DIE_AREA to 75umx100um and rerun the flow. Provide the GDSII for this run as well.