An incomplete ASMD chart for a finite state machine is shown in Fig. P8.29. The register operations are not specified, because we are interested only in designing the control logic. (a) Draw the equivalent state diagram. (b) Design the control unit with one flip-flop per state. (c) List the state table for the control unit. (d) Design the control unit with three D flip-flops, a decoder, and gates. (e) Derive a table showing the multiplexer input conditions for the control unit. (f) Design the control unit with three multiplexers, a register with three flip-flops, and a 3 x8 decoder. (g) Using the results of (f), write and verify a structural model of the controller. (h) Write and verify an RTL description of the controller. S_7 S_4 110 H 0 111 0 y 1 E FIGURE P8.29 ASMD chart for Problem 8.29 100 1 0 s_s EL 0 F H 000 101 001 010 1 + S_3 011