An I/O device transfers 16 MB/s of data into the memory of a processor over the I/O bus, which has a total data transfer capacity of 128 MB/s. The 16 MB/s of data is transferred as 4000 independent pages of 4 KB each.

Assume the processor is busy handling data during the time that each page is being transferred over the bus, which is a reasonable assumption because the time between transfers is too short to be worth doing a context switch.

If the processor operates at 200 MHz, it takes 800 cycles to initiate a DMA transaction, and 1200 cycles to respond to the device's interrupt when the DMA transfer completes, what fraction of the processor's time is spent handling the data transfer with and without DMA?