An RTM circuit (Lecture 6) has the following state: RO - 2 R1 - eR2=7R3 a During a clock cycle the inputs are x=3 (the data input) id = 1 (the load control input) at th=002 (the destination address) sa = 3 (the address of the list operand) sb -o (the address of the second) At the following clock tick, this will happen: Select one a 3 will be loaded into R2 be will be loaded into RO All registers will be set to o d. All registers will remain unchanged ec will be loaded into R2 The purpose of the clock in a digital circuit is Select one: O a. To tell the logic gates when their outputs are valid O b. To make all the flip flops update their state at the same time O c. To keep track of the time of day