Anas I mean, it needs a vhdl file, can we solve the code, cover it and deliver it

\begin{tabular}{|l|l|} Program 1.98 \\ entity power_of_2_circuit is port( x: in integer range 0 to 7; y: out integer range 1 to 128) end entity; \\ architecture logic_flow of power_of_2_circuit is \\ begin \\ y