.Answer GIVEN at the end of question. I just want to VERY DETAILED EXPLANATION for solution (5,4) with hand writing(Legible)

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5.5 For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Index Offset 63-10 9-5 5.5.1 [5] What is the ache block size (in words)? 5.5.2 [5] What is the ratio between total bits required for such a cache many blocks does the cache have? implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded. Address ??? | 00 04 10 84 A0 400 1E Dec 0 16 132 232 160 102430 1403100180 2180 5.5.4 [20] For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any) 5.5.5 [5] What is the hit ratio? 5.5.6 [5] List the final state of the cache, with each valid entry represented as a record of e, 5.5 For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Index Offset 63-10 9-5 5.5.1 [5] What is the ache block size (in words)? 5.5.2 [5] What is the ratio between total bits required for such a cache many blocks does the cache have? implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded. Address ??? | 00 04 10 84 A0 400 1E Dec 0 16 132 232 160 102430 1403100180 2180 5.5.4 [20] For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any) 5.5.5 [5] What is the hit ratio? 5.5.6 [5] List the final state of the cache, with each valid entry represented as a record of e