Answer the following question by writing codes using Verilog language: Please leave it for someone else if you don't know how to answer it

Question:

(i.e. what is required creating Counter4to3.sv, and instantiating FullAdder and HalfAdder)

The figure below shows the system we will build. All the modules have been provided, except the Counter4to3 module,. SW3] sw[1] SW[2] Sw[O] Counter4to3 a3 a2 a1 a0 FullAdder CO S HalfAdder CO S HalfAdder CO S 5'b0000 2 1 0 clk count clka7:0] Display seg[6:0 seg[6:0] dp dp Tutorial2Exercise Top Level Module Create a new Counter4to3.sv module in your project and complete it to match the diagram above. Use anl3:0 an[3:0] a 'structural modelling' style. In other words, instantiate FullAdder and HalfAdder modules and connect them as shown in the diagram. Your module should begin with the following interface module Counter4to3 (input logic a3, a2, al, a0, output logic y2, y1, y0); The figure below shows the system we will build. All the modules have been provided, except the Counter4to3 module,. SW3] sw[1] SW[2] Sw[O] Counter4to3 a3 a2 a1 a0 FullAdder CO S HalfAdder CO S HalfAdder CO S 5'b0000 2 1 0 clk count clka7:0] Display seg[6:0 seg[6:0] dp dp Tutorial2Exercise Top Level Module Create a new Counter4to3.sv module in your project and complete it to match the diagram above. Use anl3:0 an[3:0] a 'structural modelling' style. In other words, instantiate FullAdder and HalfAdder modules and connect them as shown in the diagram. Your module should begin with the following interface module Counter4to3 (input logic a3, a2, al, a0, output logic y2, y1, y0)