Answer the following questions about memory: a. What is the minimum rate in which a row refresh must be performed on a DRAM as a function of the refresh time and number of rows? b. Suppose a DRAM controller is connected to a 32-bit address bus and drives FPM DRAM memory. Suppose the data bus is 16-bits in width. To take advantage of the locality principle, which address lines should provide the row and column address?