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Answer the following questions about the Negative-Edge Triggered Master-Slave D flip-flop with PRESET_N and CLEAR_N connections, as shown in Figure 5.12 from the book.
Answer the following questions about the Negative-Edge Triggered Master-Slave D flip-flop with PRESET_N and CLEAR_N connections, as shown in Figure 5.12 from the book. Suppose that D=1 and CLK=0. Answer the following questions about Q. a) What effect does pulsing PRESET_N have on this circuit? b) What effect does pulsing CLEAR_N have on this circuit? c) What will be the value of Q if PRESET_N=0 and CLEAR_N=1? d) What will be the value of Q if PRESET_N=0 and CLEAR_N=0? e) What will be the value of Q if the clock is pulsed while CLEAR_N=1 and PRESET_N=1? Answer the following questions about the Negative-Edge Triggered Master-Slave D flip-flop with PRESET_N and CLEAR_N connections, as shown in Figure 5.12 from the book. Suppose that D=1 and CLK=0. Answer the following questions about Q. a) What effect does pulsing PRESET_N have on this circuit? b) What effect does pulsing CLEAR_N have on this circuit? c) What will be the value of Q if PRESET_N=0 and CLEAR_N=1? d) What will be the value of Q if PRESET_N=0 and CLEAR_N=0? e) What will be the value of Q if the clock is pulsed while CLEAR_N=1 and PRESET_N=1?
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Sol a If it is active low we will apply set the 0p 0 for for PRESENT to set the that is ...
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Database management systems
Authors: Raghu Ramakrishan, Johannes Gehrke, Scott Selikoff
3rd edition
72465638, 978-0072465631
