Answer the questions below given the following set of instruction:

lw $t0, 0 ($s0) add $t0, $s0, $t0 addi $t0, $t0, 16 lw $t1, 0 ($t0)

Continue to write the datapath with the 5 stages of pipeline and put a gap between instructions if there is a gap between instructions.

Assuming the processor has full forwarding, but also the instruction and data memory is not separated (meaning, both cannot be accessed at the same time), populate the following pipeline diagram using compact notation (Use S for stalls).

lw $t0, 0 ($s0)

IF

ID

EXE

MEM

WB

add $t0, $s0, $t0

addi $t0, $t0, 16

lw $t1, 0 ($t0)