Are these correct? Are there any more stalls? (Perhaps the #32 register or X0's in the LDUR functions)

Reorder the above code to reduce the stalls without changing the functionality. Assume there is no forwarding, no branch prediction, and no duplicate copies of instruction memory or data memory.

Reorder the above code to reduce the stalls without changing the functionality. Assume there is forwarding, no branch prediction, and no duplicate copies of instruction memory or data memory.

ADD X5, X3 STUR KS, Do, #24 stall SUB CBNZ A, Loop ADDI X0, Xl,#22. ADD X5, X3 STUR KS, Do, #24 stall SUB CBNZ A, Loop ADDI X0, Xl,#22