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ARM ASSEMBLY. [FIX CODE PLEASE.] 4. (30 points) Write a Software interrupts (SVC) handler that accepts the number 0x1234. When the handler sees this value,

ARM ASSEMBLY. [FIX CODE PLEASE.]

4. (30 points) Write a Software interrupts (SVC) handler that accepts the number 0x1234. When the handler sees this value, it should reverse the bits in register r9 actual SVC instruction in memory to determine its number. Be sure to set up a stack pointer in SVC mode before handling the exception.

AREA reverse, CODE, READONLY

RAMSTART EQU 0x40000000 ; Start of RAM

Mode_SVC EQU 0x13 ; Bits for Supervisor Mode

I_Bit EQU 0x80 ; When I bit is set, IRQ is disabled

F_Bit EQU 0x40 ; When F bit is set, FIQ is disabled

MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit

; enter Supervisor Mode

LDR sp, =RAMSTART ; Setup Supervisor stack pointer

SWI_Handler STMFD sp!, {r0-r3,r7,lr} ; Store off stack registers

MOV r1, sp ; Set pointer to parameters

MRS r0, SPSR ; Get SPSR

STMFD sp!, {r0} ; Store it on the stack

LDR r0, [lr, #-4] ; Get SWI instruction

BIC r0, r0, #0xFF000000 ; Extract potential 0x1234

LDR r2, =0x1234

CMP r0, r2 ; Is the SWI number 0x1234?

BLEQ ReverseR7

LDMFD sp!, {r1} ; Restore SPSR from stack

MSR SPSR_csxf, r1

LDMFD sp!, {r0-r3,r7,pc}^ ; Restore registers and return

ReverseR7 LDR r1, =32 ; 32-bit register bit counter

MOV r2, #0 ; r2 = result (will be r0)

Loop AND r3, r7, #1 ; r3 = current LSB of reg reserved

ADD r2, r3, r2, LSL #1 ; Shift left 1, result LSB is r3

MOV r7, r7, LSR #1 ; New LSB of reg to be reversed

SUBS r1, r1, #1 ; Loop 32 times

BNE Loop

MOV pc, lr ; Return from subroutine

END

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