Assignment 2 Design a synchronous counter that can be used for an elevator system of a 7th storey building as shown in Figure 1. Assume that the ground level is considered as a Oth floor. Assume that level 2 and level 7 cannot be access, since it is for authorized person only. Provide the logic circuit design with the minimum number of components and logic gates. Please design and show the level of storey in the seven segments as shown in Figure 2. 7 6 6 5 4 3 2 2 1 0 Figure 1: 7th Storey Building Elevator Synchronous Counter Decoder Figure 2: Synchronous Counter with Seven Segment Decoder