Assignment Overview

***I mainly just need help with step 3***

Assignment Overview

In this assignment you will use Vivado 2017.2 or 2017.4 Webpack to write, simulate and program an FPGA. Youll use the encoder.vhd created in Project 1 and connect it up to switches and the seven segment displays on the FPGA board. Youll also need to turn in a single PDF to Canvas (instructions at the end of the file).

Task This task is to implement an encoder where input is ONE 4-bit hex signal and the outputs are SEVEN 1- bit signals for each display segment (A-G). 1. Edit the constraints file and uncomment the lines corresponding with: ? sw ? clk ? seg ? dp ? an ? led 2. Create the top.vhd file: a) Under Flow Navigator click Add sources. b) Select Create or add design sources. c) Create top.vhd and then click Finish. d) Create inputs: ? sw ~ (15 downto 0) ? clk e) Create outputs: ? seg ~ (6 downto 0) ? dp ? an ~ (3 downto 0) ? led ~ (15 downto 0) 3. Once you have your VHDL source file (top.vhd), edit it to implement 4 encoder entities and connect the switches to the LEDs. ? Since you already have the encoder.vhd, youll just be using structural VHDL to connect multiple encoder entities to the sdd_muxer entity. ? There will be 4 instances of the encoder entity mapped to each of the FOUR 4-bit sw inputs and mapped to appropriate outputs. ? If youre feeling adventurous you can use a for generator statement or you can manually place four encoder entities. 4. Make sure its syntax error free and can be synthesized. 5. Add the top_tb.vhd file: a) Under Flow Navigator click Add sources. b) Select Create or add simulation sources. c) Add top_tb.vhd. d) Make sure simulation set is sim_1. e) Click Finish. 6. Edit ssd_muxer.vhd: a) Go to line 57-58, there will be two counter_max constants. b) Make sure the one that says FPGA is commented out and the one that says sim is uncommented. 7. Select the right simulation set: a) Under Flow Navigator click Simulation Settings. b) Under Simulation set input sim_1. c) Under Simulation top module name input top_tb. d) Click Ok. 8. Run the simulation by and check your results.

top.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity top is Port ( sw : in STD_LOGIC_VECTOR (15 downto 0); clk : in STD_LOGIC; seg : out STD_LOGIC_VECTOR (6 downto 0); dp : out STD_LOGIC; an : out STD_LOGIC_VECTOR (3 downto 0); led : out STD_LOGIC_VECTOR (15 downto 0)); end top;

architecture Behavioral of top is

begin

end Behavioral;

top_tb.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Part 1 Testbench entity top_tb is -- Port ( ); end top_tb;

architecture Behavioral of top_tb is

--this entity needs to be defined in your top.vhd file component top is Port ( sw : in STD_LOGIC_VECTOR (15 downto 0); seg : out std_logic_vector(6 downto 0); dp : out std_logic; an : out std_logic_vector(3 downto 0); led : out STD_LOGIC_VECTOR (15 downto 0); clk : in std_logic ); end component;

--clock period. Set to 100 MHz here constant clk_per : time := 10ns;

--signals to do the binding to the "top" entity signal sw : std_logic_vector(15 downto 0); signal seg : std_logic_vector(6 downto 0); signal dp : std_logic; signal an : std_logic_vector(3 downto 0); signal led : STD_LOGIC_VECTOR (15 downto 0); signal clk : std_logic := '0';

begin

uut: top port map ( sw => sw, seg => seg, dp => dp, an => an, led => led, clk => clk );

--add code here to test your outputs for correct operation (change the value of "sw") --only needs code to be added in simulation, not in the final file to be uploaded to the FPGA --this is step 7 and 8 in Part 1

--clock process, high and low for half the clock period clk_proc: process begin wait for clk_per/2; clk <= not(clk); end process clk_proc;

end Behavioral;

ssd_muxer.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity ssd_muxer is Port ( a_in : in std_logic_vector(3 downto 0); b_in : in std_logic_vector(3 downto 0); c_in : in std_logic_vector(3 downto 0); d_in : in std_logic_vector(3 downto 0); e_in : in std_logic_vector(3 downto 0); f_in : in std_logic_vector(3 downto 0); g_in : in std_logic_vector(3 downto 0); decp0_in : in std_logic; decp1_in : in std_logic; decp2_in : in std_logic; decp3_in : in std_logic; seg_out : out std_logic_vector(6 downto 0); dp_out : out std_logic; an_out : out std_logic_vector(3 downto 0); clk : in STD_LOGIC ); end ssd_muxer;

architecture Behavioral of ssd_muxer is --counter signals~ --constant counter_max : unsigned(15 downto 0) := x"8000"; --fpga constant counter_max : unsigned(15 downto 0) := x"0002"; --sim signal counter_sel : unsigned(1 downto 0) := "00"; signal counter : unsigned(15 downto 0) := x"0000";

--so we can combine and negate signal a, b, c, d : std_logic; signal e, f, g : std_logic; signal ssd0_en : std_logic; signal ssd1_en : std_logic; signal ssd2_en : std_logic; signal ssd3_en : std_logic; signal decp : std_logic;

begin -- _everything_ is active low (enabled when low) seg_out <= not(g & f & e & d & c & b & a); an_out <= not(ssd3_en & ssd2_en & ssd1_en & ssd0_en); dp_out <= not(decp);

--muxing the inputs to the output a <= a_in(0) when (counter_sel="00") else a_in(1) when (counter_sel="01") else a_in(2) when (counter_sel="10") else a_in(3);

b <= b_in(0) when (counter_sel="00") else b_in(1) when (counter_sel="01") else b_in(2) when (counter_sel="10") else b_in(3);

c <= c_in(0) when (counter_sel="00") else c_in(1) when (counter_sel="01") else c_in(2) when (counter_sel="10") else c_in(3);

d <= d_in(0) when (counter_sel="00") else d_in(1) when (counter_sel="01") else d_in(2) when (counter_sel="10") else d_in(3);

e <= e_in(0) when (counter_sel="00") else e_in(1) when (counter_sel="01") else e_in(2) when (counter_sel="10") else e_in(3);

f <= f_in(0) when (counter_sel="00") else f_in(1) when (counter_sel="01") else f_in(2) when (counter_sel="10") else f_in(3);

g <= g_in(0) when (counter_sel="00") else g_in(1) when (counter_sel="01") else g_in(2) when (counter_sel="10") else g_in(3);

--selects the decimal point for the active chip inputs decp <= decp0_in when (counter_sel="00") else decp1_in when (counter_sel="01") else decp2_in when (counter_sel="10") else decp3_in;

--selects the active low enable for the digit ssd0_en <= '1' when (counter_sel="00") else '0'; ssd1_en <= '1' when (counter_sel="01") else '0'; ssd2_en <= '1' when (counter_sel="10") else '0'; ssd3_en <= '1' when (counter_sel="11") else '0';

--simple counter proc and changes the sel counter_proc: process (clk) begin if (clk'event and clk='1') then if (counter >= counter_max) then counter <= x"0000"; counter_sel <= counter_sel + 1; else counter <= counter + 1; end if; end if; end process counter_proc;

end Behavioral;

In this assignment you will use Vivado 2017.2 or 2017.4 Webpack to write, simulate and program an FPGA. Youll use the encoder.vhd created in Project 1 and connect it up to switches and the seven segment displays on the FPGA board. Youll also need to turn in a single PDF to Canvas (instructions at the end of the file).

Task This task is to implement an encoder where input is ONE 4-bit hex signal and the outputs are SEVEN 1- bit signals for each display segment (A-G). 1. Edit the constraints file and uncomment the lines corresponding with: ? sw ? clk ? seg ? dp ? an ? led 2. Create the top.vhd file: a) Under Flow Navigator click Add sources. b) Select Create or add design sources. c) Create top.vhd and then click Finish. d) Create inputs: ? sw ~ (15 downto 0) ? clk e) Create outputs: ? seg ~ (6 downto 0) ? dp ? an ~ (3 downto 0) ? led ~ (15 downto 0) 3. Once you have your VHDL source file (top.vhd), edit it to implement 4 encoder entities and connect the switches to the LEDs. ? Since you already have the encoder.vhd, youll just be using structural VHDL to connect multiple encoder entities to the sdd_muxer entity. ? There will be 4 instances of the encoder entity mapped to each of the FOUR 4-bit sw inputs and mapped to appropriate outputs. ? If youre feeling adventurous you can use a for generator statement or you can manually place four encoder entities. 4. Make sure its syntax error free and can be synthesized. 5. Add the top_tb.vhd file: a) Under Flow Navigator click Add sources. b) Select Create or add simulation sources. c) Add top_tb.vhd. d) Make sure simulation set is sim_1. e) Click Finish. 6. Edit ssd_muxer.vhd: a) Go to line 57-58, there will be two counter_max constants. b) Make sure the one that says FPGA is commented out and the one that says sim is uncommented. 7. Select the right simulation set: a) Under Flow Navigator click Simulation Settings. b) Under Simulation set input sim_1. c) Under Simulation top module name input top_tb. d) Click Ok. 8. Run the simulation by and check your results. The expected output is shown below in Fig. 2.

top.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity top is Port ( sw : in STD_LOGIC_VECTOR (15 downto 0); clk : in STD_LOGIC; seg : out STD_LOGIC_VECTOR (6 downto 0); dp : out STD_LOGIC; an : out STD_LOGIC_VECTOR (3 downto 0); led : out STD_LOGIC_VECTOR (15 downto 0)); end top;

architecture Behavioral of top is

begin

end Behavioral;

top_tb.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Part 1 Testbench entity top_tb is -- Port ( ); end top_tb;

architecture Behavioral of top_tb is

--this entity needs to be defined in your top.vhd file component top is Port ( sw : in STD_LOGIC_VECTOR (15 downto 0); seg : out std_logic_vector(6 downto 0); dp : out std_logic; an : out std_logic_vector(3 downto 0); led : out STD_LOGIC_VECTOR (15 downto 0); clk : in std_logic ); end component;

--clock period. Set to 100 MHz here constant clk_per : time := 10ns;

--signals to do the binding to the "top" entity signal sw : std_logic_vector(15 downto 0); signal seg : std_logic_vector(6 downto 0); signal dp : std_logic; signal an : std_logic_vector(3 downto 0); signal led : STD_LOGIC_VECTOR (15 downto 0); signal clk : std_logic := '0';

begin

uut: top port map ( sw => sw, seg => seg, dp => dp, an => an, led => led, clk => clk );

--add code here to test your outputs for correct operation (change the value of "sw") --only needs code to be added in simulation, not in the final file to be uploaded to the FPGA --this is step 7 and 8 in Part 1

--clock process, high and low for half the clock period clk_proc: process begin wait for clk_per/2; clk <= not(clk); end process clk_proc;

end Behavioral;

ssd_muxer.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity ssd_muxer is Port ( a_in : in std_logic_vector(3 downto 0); b_in : in std_logic_vector(3 downto 0); c_in : in std_logic_vector(3 downto 0); d_in : in std_logic_vector(3 downto 0); e_in : in std_logic_vector(3 downto 0); f_in : in std_logic_vector(3 downto 0); g_in : in std_logic_vector(3 downto 0); decp0_in : in std_logic; decp1_in : in std_logic; decp2_in : in std_logic; decp3_in : in std_logic; seg_out : out std_logic_vector(6 downto 0); dp_out : out std_logic; an_out : out std_logic_vector(3 downto 0); clk : in STD_LOGIC ); end ssd_muxer;

architecture Behavioral of ssd_muxer is --counter signals~ --constant counter_max : unsigned(15 downto 0) := x"8000"; --fpga constant counter_max : unsigned(15 downto 0) := x"0002"; --sim signal counter_sel : unsigned(1 downto 0) := "00"; signal counter : unsigned(15 downto 0) := x"0000";

--so we can combine and negate signal a, b, c, d : std_logic; signal e, f, g : std_logic; signal ssd0_en : std_logic; signal ssd1_en : std_logic; signal ssd2_en : std_logic; signal ssd3_en : std_logic; signal decp : std_logic;

begin -- _everything_ is active low (enabled when low) seg_out <= not(g & f & e & d & c & b & a); an_out <= not(ssd3_en & ssd2_en & ssd1_en & ssd0_en); dp_out <= not(decp);

--muxing the inputs to the output a <= a_in(0) when (counter_sel="00") else a_in(1) when (counter_sel="01") else a_in(2) when (counter_sel="10") else a_in(3);

b <= b_in(0) when (counter_sel="00") else b_in(1) when (counter_sel="01") else b_in(2) when (counter_sel="10") else b_in(3);

c <= c_in(0) when (counter_sel="00") else c_in(1) when (counter_sel="01") else c_in(2) when (counter_sel="10") else c_in(3);

d <= d_in(0) when (counter_sel="00") else d_in(1) when (counter_sel="01") else d_in(2) when (counter_sel="10") else d_in(3);

e <= e_in(0) when (counter_sel="00") else e_in(1) when (counter_sel="01") else e_in(2) when (counter_sel="10") else e_in(3);

f <= f_in(0) when (counter_sel="00") else f_in(1) when (counter_sel="01") else f_in(2) when (counter_sel="10") else f_in(3);

g <= g_in(0) when (counter_sel="00") else g_in(1) when (counter_sel="01") else g_in(2) when (counter_sel="10") else g_in(3);

--selects the decimal point for the active chip inputs decp <= decp0_in when (counter_sel="00") else decp1_in when (counter_sel="01") else decp2_in when (counter_sel="10") else decp3_in;

--selects the active low enable for the digit ssd0_en <= '1' when (counter_sel="00") else '0'; ssd1_en <= '1' when (counter_sel="01") else '0'; ssd2_en <= '1' when (counter_sel="10") else '0'; ssd3_en <= '1' when (counter_sel="11") else '0';

--simple counter proc and changes the sel counter_proc: process (clk) begin if (clk'event and clk='1') then if (counter >= counter_max) then counter <= x"0000"; counter_sel <= counter_sel + 1; else counter <= counter + 1; end if; end if; end process counter_proc;

end Behavioral;