Assistance would be greatly appreciated

1) (Based on C.1 of the book, Page C-71) [6pts] Use the following code fragment: Loop: |x9, 0(x2) |x4, x9,x9 |x10.0(x1) add $10,x10, x4 sd *10.0(x1) 12, x2, 4 sub x5, x2, x3 S, Loop I b nez 2) (Based on C.3 of the book, Page C-73)[4pts] We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 9.5 ns. After the stages were split, the measured times were IF, 1.3 ns; ID, 2.2 ns; EX, 1.1 ns; MEM, 2.6 ns; and WB, 2.3 ns. The pipeline register delay is 0.4 ns. a. What is the clock cycle time of the 5-stage pipelined machine? b. If there are two stalls every 5 instructions, what is the CPI of the new machine? c. What is the speedup of the pipelined machine over the single-cycle machine? d. If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine