5. Assume a 4-way set-associative cache with 64 cache sets, 4 words per block with write through- no write allocate rule. Fill in the appropriate information for the following memory references. (20 pts.)

Suppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 500 ps and a CPI of 3.0 for some program, and computer B has a clock cycle time of 800ps and a CPI of 4.2 for the same program. Which computer is faster for this program and by how much

R/W

Addr

Tag

Index

Offset

Result

Update Cache?

W

10111001000

R

10111001100

R

111001100

W

111001000

R

100111001000

R

100111001100

W

110111001100

R

110111001000