Assume a computer has L1 and L2 caches. The cache blocks consist of 8 words. Assume that the hit rate is the same for both caches and that it is equal to 0.95 for instructions and 0.90 for data. Assume also that the times needed to access an 8-word block in these caches are C1 = 1 cycle and C2 = 10 cycles.

What is the average access time experienced by the processor if the main memory uses interleaving? The memory is built with relatively slow DRAM chips that allow the first word to be accessed in 8 cycles, but subsequent words of the block are accessed in 4 clock cycles per word. Also, one clock cycle is needed to send one word to the cache.

What is the average access time if the main memory is not interleaved?

What is the improvement obtained with interleaving?