Assume a five-stage single-pipeline microarchite cture (fetch, decode, execute, memory, write- back) and the code in Figure below. All ops are one cycle except LW and SW, which are 12 cycles, and branches, which are 1 +1 cycles. There is no forwarding. Show the phases of each instruction per clock cycle for one iteration of the loop. (30) a. How many clock cycles per loop iteration are lost to branch overhead? 3. b. Assume a static branch predictor, capable of recognizing a backward branch in the Decode stage. Now how many clock cycles are wasted on branch overhead? C. Assume a dynamic branch predictor. How many cycles are lost on a correct predictioni? oop: 1w x1.0(x2) addi SW addi sub bnz x1.x1.1 x1.0(x2) x2.x2.4 x4.x3.x2 x4.Loop