Assume a full$-$bypass circuit. Draw the pipeline chart showing all the bypass flow and register

access flow on the diagram, for the following MIPS code sequence. Assume there are $2$ MUL ALUs

and they require $3$ execute cycles, whereas the rest of the ALUs take $1$ cycle to execute.

LOAD R$1,$ R$2,$ #$100$

MUL R$2,$ R$1,$ R$3$

MUL R$1,$ R$1,$ R$2$

STORE R$1$ R$2$#$200$

XOR R$2,$ R$1,$ R$3$