Assume a GPU architecture that contains $10$ SIMD processors.

Each SIMD instruction has a width of $32$ and each SIMD processor contains $8$ lanes

for single$-$precision arithmetic and load$/$store instructions, meaning that each nondiverged

SIMDinstruction can produce $32$ results every $4$ cycles. Assume a kernel that

has divergent branches that causes, on average, $80\%$ of threads to be active. Assume

that $70\%$ of all SIMD instructions executed are single$-$precision arithmetic and $20\%$

are load$/$store$.$ Because not all memory latencies are covered, assume an average

SIMD instruction issue rate of $0\mathrm{.}85.$ Assume that the GPU has a clock speed of

$1\mathrm{.}5$ GHz$.$