assume a microcontroller with sixteen address lines - assume 16 address bits, A15 most significant.

3) Making the same assumptions as above, use a single 138 3-to-8 decoder and as few NAND gates as possible to design a memory circuit to fully decode the following address space: Unit size/type Start Address U1 U2 U3 2k Ram 2k RAM 2k RAM $6800 SFe00 $7800 and to partially decode, via a 2-level scheme using an additional 1/2 of a '139 four 256 byte I/0 devices having the following starting addresses: I/O 0 $6000 I/0 1 $6100 I/O 2 $6200 I/0 3 $6300 3) Making the same assumptions as above, use a single 138 3-to-8 decoder and as few NAND gates as possible to design a memory circuit to fully decode the following address space: Unit size/type Start Address U1 U2 U3 2k Ram 2k RAM 2k RAM $6800 SFe00 $7800 and to partially decode, via a 2-level scheme using an additional 1/2 of a '139 four 256 byte I/0 devices having the following starting addresses: I/O 0 $6000 I/0 1 $6100 I/O 2 $6200 I/0 3 $6300