Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence

ADD $T0, $T1, $T3 ADDI $S1, $S1, 4 LW $S0, 0($S1) SUB $S5, $S0, $T0 AND $T3, $T4, $S5 SW $S5, 0($S1) MULT $S2, $S6, $T3 SUB $T6, $T7, $S6

a)How many stalls (in terms of the number of stall clock cycles) will the processor experience if it does not have any forwarding unit to reduce or eliminate pipeline stalls? (Assume that the write back step of an earlier instruction and the instruction decode step of a subsequent dependent instruction can happen in the same clock cycle).

b)Calculate the total number of clock cycles needed to complete executing the instruction sequence.

c)If the processor has a forwarding unit to reduce different kinds of data hazards, what would be the total number of stall cycles to execute the same instruction sequence?

d)If the manufacturer does not upgrade the processor to have a forwarding unit, but an optimizing compiler reduces hazards by altering the instruction sequence, what will be the minimal number of stall cycles?