Assume byte-addressable main memory has address size of 24 bits. For a 2-way-setassociative -mapped cache design, the following bits of the address are used to access the cache. Tag 13 bits (i) What is the cache line size in bytes? (ii) How many entries does the cache have? (iii) What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded. Addresses: $0 \quad 4 \quad 4 \quad 32 \quad 64 \quad 128 \quad 256 \quad 512 \quad 1024 \quad 2014 Squad \quad 4 \quad 32$ (iv) How many blocks are replaced? (v) What is the hit ratio? (vi) Show the state of cache memory at the end (the cache lines containing blocks of main memory) cs.vs. 1142||