Assume clock cycle is 9ns, cell delay of each register is 1ns, the setup of each register is 1ns. - Calculate the setup time slack of the Path 1 and Path 2. Do path 1 and path 2 satisfy the setup timing requirement? If not, which path can /cannot meet the timing? Can you figure out a simple way to fix the timing issues in those two paths: Make sure the timing slacks for path 1 and path 2 are both +0.5ns? (Hint, tune one of the Tck-9ns Tsetup-lns T FFcell delay -Ins 6.5ns ath 2 D Q 5.5ns D Q D Q Path 1 Ick delay l_2ns ck, delay,-2ns ck, delay,-1 ns Assume clock cycle is 9ns, cell delay of each register is 1ns, the setup of each register is 1ns. - Calculate the setup time slack of the Path 1 and Path 2. Do path 1 and path 2 satisfy the setup timing requirement? If not, which path can /cannot meet the timing? Can you figure out a simple way to fix the timing issues in those two paths: Make sure the timing slacks for path 1 and path 2 are both +0.5ns? (Hint, tune one of the Tck-9ns Tsetup-lns T FFcell delay -Ins 6.5ns ath 2 D Q 5.5ns D Q D Q Path 1 Ick delay l_2ns ck, delay,-2ns ck, delay,-1 ns