Assume for a given processor the $\frac{C}{P}$I of arithmetic instructions is $2,$ the $\frac{C}{P}$I of load$/$store

instructions is $8,$ and the $\frac{C}{P}$I of branch instructions is $4.$ Assume a program has the following

instruction breakdowns: $450$ million arithmetic instructions, $300$ million load store instructions, and

$150$ million branch instructions.

a$.$ Suppose that new more powerful arithmetic instructions are added to the instruction set. On

average, through the use of these more powerful arithmetic instructions, we can reduce the number

of arithmetic instructions needed to execute a program by $25\%?$

b$.$ For a$,$ the cost of increasing the clock cycle time is only $10\%$ is this a good design choice? Why?

c$.$ Suppose that we find a way to double the performance of arithmetic instructions. What is the

overall speedup of our machine?

d$.$ What if we improve the performance of arithmetic instructions by $10$ times?

Assume that for a given program $65\%$ of the executed instructions are arithmetic, $20\%$ are

load$/$store$,$ and $15\%$ are branch. Given the instruction mix and the assumption that an arithmetic

instruction requires $2$ cycles a load store instruction requires $6$ cycles and a branch instruction

requires $3$ cycles find the average $\frac{C}{P}$I $.$

a$.$ For a $25\%$ improvement in performance how many cycles on average may an arithmetic

instruction take if a load$/$store and branch instructions are not improved?

b$.$ For a $50\%$ improvement in performance how many cycles on average may an arithmetic

instruction take if load$/$store and branch instructions are not improved?

c$.$ For a $5\%$ improvement in performance how many cycles must a branch instruction take if

load$/$store and arithmetic instructions are not improved?

d$.$ For a $5\%$ improvement in performance how many cycles must a load$/$store instruction take if

branch and arithmetic instructions are not improved?