Assume that individual pipeline stages of a five-stage pipelined architecture take the following latencies: ID EX MEM WB 220ps 250ps a. What would be the clock cycle time in a pipelined and single-cycle processor? What would be the total latency of an LW instruction in a pipelined and single-cycle processor? b. 2. Assume that you have a pipelined processor that has 10 pipeline stages a. For cach instruction execution, how many cycles will be taken? b. You want to execute a program having 20 instructions on this processor. How many cycles will be taken to finish the program