Assume that individual stages of the data path have the following latencies: IF:350ps ID:450ps EX:250ps MEM:400ps WB:200ps Also, assume that instructions executed by the processor are broken down as follows: alu:45% beq:20% lw: 20% sw: 15% a) What is the clock cycle time in a pipelined and non-pipelined proces- b) What is the total latency of an LW instruction in a pipelined and non- c) If we can split one stage of the pipelined data path into two new stages sor? pipelined processor? (4 points) each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?(4 points) d) Assuming there are no stalls or hazards, what is the utilization of the lata memory access? (2 points) e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the ?Registers? unit?(2 points) ) Instead of a single-cyle organization, we can luse a multi-cyde or ganization where each instruction takes multiple cycles but one instructio finishes before another is fetched. In this organization, an instruction only goes through stages it actually needs (e.g., ST only takes 4 cycles because it does not need the WB stage). Compare the execution times with pipelined single-cycle, non-pipelined single-cycle and multi-cycle.(Give the formula wil