Assume that we have a 5-stage pipeline that has no branch delay slot and no particular branch prediction mechansim employed. Thus, when we have branch instruction, we have to introduce pipeline bubbles until the branch outcome is known For this question, we assume that the branch outcome is known at the end of third pipeline stage (ie, X) a) Below is an affect of taken branch on the pipeline. ccl cc2 cc3 cc4 cc5cc6 cc7 cc8 cc9 (clock cycle) MEM WB Taken branch IFID inst+1 inst+2 inst+3 EX IF stall IF ID EX MEM WB stall stal IF ID EX MEM WB stall stall IF ID EX MEM WB Please, explain what is happening in the pipeline. Why do we see that inst+1 stalls at cycle 3, and there is a another IF at cycle 4 for inst+1? What is happening for inst+2 and inst+3? b) Below is an affect of not-taken branch on the pipeline ccl cc2 cc3 cc4 cc5 cc6 cc7 cc8 cc9 (clock cycle) NT branch IF ID EX MEM WB inst+1 inst+2 inst+3 IF stall D EX MEM WB stall IF ID EX MEM WB stall IF ID EX MEM WB Please, explain what is happening in the pipeline. Why don't we see the behaivor that we saw inst+1 in taken branch scenario? Why does inst+1 stall at cycle 3, and continue with ID stage at cycle 4? What is happening for inst+2 and inst+3