Assume that X1 is initialized to 11 and X2 is initialized to 22 Suppose you executed the code below on a version of the pipeline from diagram below What would the final values of register X5 be Assume the register file is written at the beginning of the cycle and read at the end of a cycle Therefore, an ID stage will return the results of a WB state occurring during the same cycle ADDI X1, X2, 5 ADD X3, X1, X2 ADDI X4, X1, 15 ADD X5, X1, X1 ALU Data Sign 64 GURE 4 40 The corrected pipelined datapath to handle the load instruction properly The write register number now omes from the MEM WB pipeline register along with the data The register number is passed from the ID pipe stage until it reaches the MEM VB pipeline register, adding five more bits to the last three pipeline registers This new path is shown in color

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Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline

Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from diagram below. What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. ADDI X1, X2, #5

ADD X3, X1, X2

ADDI X4, X1, #15

ADD X5, X1, X1 image text in transcribed

ALU Data Sign 64 GURE 4.40 The corrected pipelined datapath to handle the load instruction properly. The write register number now omes from the MEM/WB pipeline register along with the data. The register number is passed from the ID pipe stage until it reaches the MEM/ VB pipeline register, adding five more bits to the last three pipeline registers. This new path is shown in color