Assume that you have a system that contains a 16-word cache (C=16). Consider the following RISCV assembly code. Please fill out the chart.

Assume that you have a system that contains a 16-word cache (C=16). Consider the following RISCV assembly code addi to, zero, 4 addi 50 , zero, 0 loop: beq to, zero, done Iw t1,030(so) Iw t2, 0x70(so) Iw t3,054(so) Iw t3,050(so) addi t0, t0, 1 j loop done: Partl: Direct Mapped Cache, b=1 word 2)Place every instruction's data in the correct set in the cache. Also, determine what kind of miss the instruction faces. Assume that you have a system that contains a 16-word cache (C=16). Consider the following RISCV assembly code addi to, zero, 4 addi 50 , zero, 0 loop: beq to, zero, done Iw t1,030(so) Iw t2, 0x70(so) Iw t3,054(so) Iw t3,050(so) addi t0, t0, 1 j loop done: Partl: Direct Mapped Cache, b=1 word 2)Place every instruction's data in the correct set in the cache. Also, determine what kind of miss the instruction faces