Assume the following:

Function units are not pipelined.

There is no forwarding between function units; results are communicated by the CDB.

The execution stage (EX) does both the effective address calculation and the memory access for loads and stores. Thus the pipeline is IF / ID / IS / EX / WB.

Loads take 1 clock cycle.

The issue (IS) and write result (WB) stages each take 1 clock cycle.

There are 5 load buffer slots and 5 store buffer slots.

Assume that the BNEZ instruction takes one clock cycle

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FU Type	Cycles in EX	Numbers of FUs	Number of Reservation Stations
Integer	1	1	5
FP Adder	10	1	3
FP Multiplier	15	1	2

For this problem use the two-issue Tomasulo MIPS pipeline with the above latencies. SHow the number of stall cycles for each instruction and what clock cycle each intruction begins execution for 3 iterations of the loop. How many cycles does each loop iteration take. Show answer in form of a table with the following headers: Iteration, Instruction, Issues, Exectures, Memory Access, Write CDB, any comments.

For the following parts:

(A) With speculation; and assume the outcome of branch instruction is correctly predicted. (B) Assume there is an integer ALU for address calculation; and another integer ALU for branch and all other integer operations. (3) If the first instruction in an issue packet is a branch instruction, only this branch instruction can be issued in this cycle. (C) Up to two instruct ions can be committed per cycle. (D) There are two CDBs. (E) For load/store, EX is for address calculation . (F) Only show the first two iterations (G) Only show the timing starting from the Issue stage. (H) Assume there is no forwarding