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Assume the following information: The average memory penalty for a cache miss is 72 clock cycles. Miss rate is 2.9%. 20% of instructions are data

Assume the following information:

The average memory penalty for a cache miss is 72 clock cycles.

Miss rate is 2.9%.

20% of instructions are data transfer instructions (loads/stores).

CPI for a perfect cache is 1.5 clock cycles.

The total number of instructions executed is IC.

Answer the following questions:

a. What is the total number of memory stall cycles?

b. What is the number of Memory Stall Cycles (MSC) per instruction?

c. What is the average CPI?

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